Section 2 UFS Hardware Interface

第二节 UFS硬件接口

Unlike eMMC parallel 8bit data bus, UFS is utilize MIPI M-PHY’s serial bus protocol. In UFS，there are up to two lanes, which is composed of a pair of differential signals for data transmitting. These differential signals are not bi-direction like eMMC single-ended data I/O. This is also the reason that UFS could do full-duplex data transmission while eMMC could only do half-duplex.

跟eMMC的8bite并行总线不同，UFS使用了MIPI M-PHY的串型总线协议。在UFS里总共有最多两个通路，每个通路是由一对差分信号组成来传输数据。这些差分信号跟eMMC里的单端输入输出数据口不一样，它们不是双向的。这也是为什么UFS可以做到全双工数据传输，而eMMC只能是半双工。

This pair of differential signals is symmetric, one is from Host to Device, and the other one is opposite from Device to Host. The point close to the source (aka Transmitter) is called Tx, and that close to target (aka Receiver) is called Rx. This is the reason that for each signal, we will have both Tx and Rx based on which side (Host or Device) we need to emphasize.

这一对差分信号是对称的，一个从主机端到器件端，而另一个相反是从器件端到主机端。离源端（也叫发送端）近的点被称为Tx，而那个离目的端（也叫接收端）近的点被称为Rx。 这也是为什么每一个信号线，根据我们要强调哪一方（主机还是器件），我们都有Tx和Rx的原因。

Original MIPI M-PHY specification allows asymmetric structure and more than two lanes, which means there could be multiple Host Tx in one Lane and less or even no Device, or vice versa. In current UFS real usage case, the options could only be one lane or two lanes, one Host Tx and One device Tx is a must for each lane.

原生的MIPI M-PHY协议允许非对称的结构以及允许多于两个通路，这个意味着有可能出现在一个通路中有多个主机以及很少甚者没有器件/主机，或者相反也可以。在现在的UFS实际使用场景中，选择只有一个通路或者两个通路，而且在一个通路中必须要有一个主机Tx以及一个器件Tx。

UFS transmission data rate (~24Gbps for High-Speed Gear 5 HS-G5) is much higher than eMMC transmission data rate (400MB/s, 3.2Gbps), this is the main reason that UFS use differential signals for data transmission instead of single ended signals. Each Differential signal is combined by two opposite single ended line, one is masked as letter p(stand for Positive) or letter t(stand for Ture), while another one is marked as letter n(stand for Negative) or letter c(stand for Complement). The benefit of differential signal is to reduce or eliminate the transmission noise. Differential signal is widely used in High-Speed transmission.

UFS传输数据线速率（高速速度5档HS-G5的约24吉比特每秒）比eMMC传输数据速率（400兆比特每秒，3.2吉比特每秒）的速度要高得多，这也是为什么UFS使用差分信号传输数据而不是单端信号的原因。每一个差分信号是由一对相反的单端信号组成，一个被标记成字母p（代表正）或者字母t（代表真），而另一个被标记成字母n（代表负）或者字母c（代表补）。使用差分信号的好处是减少或者抵消传输噪声。差分信号在高速传输中广泛应用。

Besides these High-Speed Differential signals, UFS also has two low speed single-ended signals, one is reference clock (Ref-Clk), the other one is Hardware Reset (nReset, suffix letter n means this signal is low level voltage valid，could be symbol # as well). Both these two signals are from Host to device.

除了这些高速差分信号，UFS还有两根低速的单端信号，一个是参考时钟（Ref-Clk），另一个是硬件复位（nReset，前缀字母n代表低电平有效，也可用是符号#）。这两个信号都是从主机端到器件端。

UFS reference clock is less than 100Mhz (19.2Mhz, 26Mhz, 38.4Mhz, or 52Mhz), much lower than the actual data transmitting data rate. The name of Reference is because it is only used for data sending synchronization reference. While for data receiving, the receiver for both sides will use Clock Data Recover (aka CDR) to extract the clock.

UFS的参考时钟小于100兆赫兹（19.2兆赫兹, 26兆赫兹, 38.4兆赫兹, or 52兆赫兹），这个比实际数据传输速率要低得多。参考这个名字的原因是因为这个时钟只用于发送数据时做同步参考。而对于数据接收，两边的接收端会利用时钟数据恢复（也叫CDR）来提取时钟。

This is quite different from the clock in eMMC. eMMC clock will be a main factor for synchronization of receiver data sampling, and clock frequency is always the same as the single data rate, while for Dual Date rate, both rising and falling edge are used for sampling, hence data rate is double compared to clock frequency. This is why data receiving sampling data setup time and hold time is calculated based on the edge of such synchronized clock. The highest eMMC clock frequency is 200Mhz。

这个和eMMC的时钟非常不一样。eMMC的时钟是接收端数据采样同步的主要因素，而且总是和单沿数据传输速率，而对于双沿数据传输，上升沿和下降沿都用于采样，所以数据传输速率相比较时钟频率而翻倍了。这也是数据接收采样的数据建立时间和保持时间是基于这个同步时钟的边沿来计算。eMMC最高的时钟频率是200兆赫兹。

UFS reference clock frequency is even lower eMMC synchronized clock. But it does not mean no need to care about the accuracy of UFS Ref-Clk. On the contrary, in order to ensure the high-speed transmitting, the Ref-Clk requirement is kind of critical. It does not need only check the frequency bias from time domain (<±150PPM), but also need to check the phase noise (<-66dBc) from Frequency domain.

UFS的参考时钟甚至比eMMC的同步时钟还低。但是这个并不意味着不需要关心UFS参考时钟的准确性。相反，为了确保高速传输，参考时钟的要求还有点苛刻，它不仅要求从时域上检查频率的偏移（小于正负百万分之150），而且还要从频域上检查相位噪声（小于-66dBc）。

Hardware Reset is a mandatory signal in UFS. This is also different with eMMC in which Hardware Reset is optional. It is activated low and device start to do Hardware reset at its rising edge.

硬件复位性好在UFS里是强制要求的，这个也和eMMC不同，eMMC里硬件复位是可选的。这个是在低电平生效，UFS器件是在信号的上升沿开始做硬件复位。

We will cover detail requirement for signals above in UFS signal integrity chapter.

我们将会在UFS的信号完整性的章节里面解释这些信号的细节。

Similar to eMMC, UFS also has VCCQ and VCC, there is one additional VCCQ2. VCCQ 1.2V and VCC 2.5V are designed for data rate up to High-Speed Gear 5 (～24Gbps，UFS4.0 Specification HS-G5). While VCCQ2 1.8V and VCC3V are designed only for data rate up to High-Speed Gear 3 (～6Gbps，UFS2.X specification HS-G3).

和eMMC类似，UFS也有VCCQ和VCC，而且还有增加一个VCCQ2。1.2V的VCCQ和2.5V的VCC是设计用于支持数据传输最高到高速5档（约24吉比特每秒，UFS4.0规范HS-G5）。而1.8V的VCCQ2 1.8V和3V的VCC是设计支持数据传输最高只能到高速3档（6吉比特每秒，UFS2.x规范HS-G3）。

There is no need to supply both 1.8V VCCQ2 and 1.2V VCCQ, UFS device that use 1.2V VCCQ to support higher Gear could also be compatible to support lower Gear as 1.8V VCCQ2. Unless the UFS device only support up to HS-G3, otherwise we do not need 1.8V VCCQ2. Most UFS device used now are supporting HS-G4 or even HS-G5, hence VCCQ 1.2V and VCC2.5V are dominant in design. One more thing need to be noted is that, VCC2.5V and VCC 3V share the same power trail. In some design that could use both UFS2.x device (up to HS-G3) and UFS3.x/UFS4.x device (up to higher than HS-G3), when system power up with 3V VCC, once UFS host identify that UFS device has got capability to support higher Gear, it need switch the 3V VCC to lower 2.5V voltage.

没有必要同时提供1.8V VCCQ2和1.2V VCCQ, UFS用1.2V的VCCQ来支持高速档位，也可以兼容1.8V VCCQ2支持的低速挡位。除非UFS器件只支持最高到高速3档，否则我们不需要用1.8V VCCQ2。现在几乎绝大多数用到的UFS器件都支持高速4档甚者高速5档，所以1.2V VCCQ和2.5V VCC在设计中占据主导。还需要注意的是，2.5V VCC和3V VCC是在一条电源线上。在一些既可以用UFS2.x器件（最高到HS-G3）也可以用UFS3.x/UFS4.x器件（最高档位高于HS-G3）的设计中，当系统以3V VCC启动时，一旦UFS主机确认了UFS器件有能力支持更高的档位，它需要把3V VCC切换到2.5V VCC。